The present invention relates to semiconductor device manufacturing, and more particularly to a method of fabricating a metal oxide semiconductor field effect transistor (MOSFET) in which the gate and source/drain regions are independently doped in a self-aligned manner after the gate stack has been etched. The method of the present invention does not affect line width control, and no additional lithography steps are required.
In today""s most advanced semiconductor devices, the gate implant is also received by the source/drain regions. Typically, the maximum amount of dopant that the gate can receive is limited by the amount that the source/drain regions can tolerate. For example, current state-of-the-art NFETs use phosphorus for the source/drain regions. If too much phosphorus is implanted into the source/drain regions, then lateral phosphorus diffusion may be excessive causing degraded short channel effects. On the contrary, implanting high doses of phosphorus (on the order of about 5E15 cmxe2x88x922 or greater) into the gate reduces the gate depletion effect and improves the device characteristics.
In some prior art processes, wider source/drain spacers are used to accommodate a higher dose of phosphorus into the source/drain regions. However, this causes the series resistance of the transistor to significantly increase.
If arsenic is used for the source/drain doping, achieving comparable gate activation as phosphorus is difficult for the same thermal cycle. In order to achieve maximum flexibility in achieving the least poly depletion and best short channel effect control, independent doping of the source/drain regions and the gate regions is desirable.
It would thus be beneficial if a method would be developed that was capable of independent doping of the gate region and the source/drain regions. Such a method would achieve improvements in the gate region of the device without negatively impacting the source/drain regions of the device.
One possible prior art approach for independent doping of the gate and the source/drain regions includes the use of a so-called gate predoping scheme. A typical gate predoping scheme of the prior art includes the steps of:
(i) depositing polysilicon onto a surface of a gate dielectric which is formed atop a semiconductor substrate;
(ii) using a first lithographic step to block the PFET region;
(iii) implanting ions into the NFET polysilicon material;
(iv) stripping the resist employed in step (ii);
(v) using a second lithographic step to block the NFET region;
(vi) implanting ions into the PFET polysilicon material;
(vii) stripping of the resist; and
(viii) etching the gate stack region.
In this prior art process, an activation annealing step is typically performed between steps (vii) and (viii) mentioned above.
A major disadvantage of this prior art integration scheme is that the implants are performed before the gate stack has been etched. This leads to poor line width control since the P-type polysilicon will etch differently than the N-type polysilicon. Also, if the implant condition is changed, the gate etch steps needs to be re-optimized again since a different doping in the gate region will change the etch characteristics. Another major disadvantage of the aforementioned prior art gate predoping scheme is that it requires two additional lithography steps, e.g., steps (ii) and (v) mentioned-above, prior to etching of the gate region. A yet further disadvantage of this prior art process is that the different etching rates may results in recessing a portion of the substrate.
In view of the above drawbacks with prior art methods, there is a continued need for providing a method which is capable of independent doping of the gate and the source/drain regions that will allow for optimizing the doping in the gate and source/drain regions independently so that improved device characteristics can be achieved without the compromise between gate depletion and series resistance.
One object of the present invention is to provide a method of fabricating a MOSFET device which is capable of independent doping of the gate and the source/drain regions.
A further object of the present invention is to provide a method of fabricating a MOSFET device which has reduced gate depletion, improved device characteristics and limited lateral diffusion of dopant in the source/drain regions and the source/drain extension regions.
Another object of the present invention is to provide a method of fabricating a MOSFET device which has improved series resistance and line width control.
A yet further object of the present invention is to provide a method of fabricating a MOSFET device in which gate predoping is avoided and the number of lithographic steps is reduced.
These and other objects and advantages are achieved in the present invention by applying a planarizing organic film to a semiconductor structure after the gate regions have been etched. Since the film is planarizing, the source/drain diffusion regions as well as the source/drain extension regions are covered with a thick amount of film, while the gate region is covered with a very thin amount of the material. A particular attractive choice for the planarizing film is an antireflective coating such as AR7 or DUV 30, each sold by Brewer Scientific, LTD.
With the proper film thickness and ion implantation conditions, along with a possible reactive-ion etch back to completely clear the top horizontal surface of each gate region, the gate regions may be implanted while the source/drain extension regions and source/drain diffusion regions are being protected from the implant.
One aspect of the present invention thus relates to a method of fabricating a MOSFET device which comprises the steps of:
(a) forming a plurality of patterned gate stacks atop a layer of gate dielectric material;
(b) forming a first planarizing organic film on said gate dielectric material and abutting vertical sidewalls of said patterned gate stacks, said planarizing organic film not being present on top, horizontal surfaces of each of said patterned gate stacks;
(c) blocking some of the plurality of patterned gate stacks with a first resist, while leaving other patterned gate stacks of said plurality unblocked;
(d) implanting first ions into said unblocked patterned gate stacks;
(e) removing said first resist and said first planarizing organic film, applying a second planarizing film and blocking said previously unblocked patterned gate stacks with a second resist;
(f) implanting second ions into said patterned gate stacks that are not blocked by said second resist; and
(g) removing said second resist and said second planarizing organic film.
In one embodiment of the present invention, the planarizing organic film of step (b) is formed on exposed surfaces of a semiconductor structure which do not contain a patterned gate region, i.e., patterned gate stack formed atop a patterned gate dielectric.
Note that source/drain regions and source/drain extension regions may be formed prior to performing step (b) above, after step (d) and step (f), or after step (g). When the source/drain regions and source/drain extensions are formed, it may be necessary to form sidewall spacers on the vertical sidewalls of each patterned gate stack region. In one preferred embodiment of the present invention, source/drain regions and/or source/drain extension regions are implanted after steps (d) or (f). Before the implants, the planarizing film is selectively etched with respect to the resist, gate and substrate.
In the present invention, the first ions employed in step (d) may be the same or different from the second ions employed in step (f). In a preferred embodiment of the present invention, the first ions are different from the second ions. Note that in some embodiments, the ions used in steps (d) and (f) are the same, but different ion dosages are employed in each step so as to form doped gate regions having different ion concentrations.